Video signal processing system

ABSTRACT

A video signal processing system for processing a video data V IN  and graphic data D μP  includes a filter unit, which receives the video data V IN . The filter unit filters the video data V IN  to convert the video data V IN  into video pictures formated with a different number of columns and/or lines, and provides a filtered video signal indicative thereof. The filter unit buffers individual pixels and/or lines in a first memory device. A second memory device receives and stores the graphic data D μP  and the filtered video signal and provides stored signals indicative thereof. A third memory device is connected to the second memory, and stores data received from the second memory device. A mixing unit receives and mixes the stored graphic data and the stored filtered video data to provide a video output signal V OUT .

BACKGROUND OF THE INVENTION

[0001] The invention relates to a video signal processing system, and inparticular to a system for processing both video data and graphic datato provide a mixed output signal.

[0002] Video signal processing systems often include a filter unit thatconverts video pictures from a first format to a second format. Forexample, the first format may be coded in accordance with the digitalstudio standard of the International Telecommunications Union UIT-R (orof the Comite Consultatif International des Radiocommunications: CCIR)601. An example of converting from a first format to a second format isthe conversion from a PAL 16×9 picture format with 720 pixels per line(P/L) and 576 lines (L), into the National Television System Committee(NTSC) 16×9 picture format, with 480 pixels per line and 480 lines.

[0003] In addition, video signal processing systems often include acomputing unit for mixing video and graphic pictures (e.g., layering andalpha-blending). The computing unit for mixing may weight differentpictures by adjustable factors (i.e., alpha blending), so thattransparent pictures can be displayed by combining and superposing theimages (i.e., layering). For example, transparent buttons may beinserted while the original video picture continues to be visible in thebackground.

[0004] At this time, such systems exist only as individual components. Adisadvantage of combining such systems is the amount of memory requiredto filter and mix video and graphic pictures.

[0005] Therefore, there is a need for a memory efficient video signalprocessing system capable of converting video signals from a firstformat to second format, and mixing several pictures.

SUMMARY OF THE INVENTION

[0006] Briefly, according to an aspect of the present invention, a videosignal processing system for processing a video data V_(IN) and graphicdata D_(μP) includes a filter unit, which receives the video dataV_(IN). The filter unit filters the video data V_(IN) to convert thevideo data V_(IN) into video pictures formated with a different numberof columns and/or lines, and provides a filtered video signal indicativethereof. The filter unit buffers individual pixels and/or lines in afirst memory device. A second memory device receives and stores thegraphic data D_(μP) and the filtered video signal and provides storedsignals indicative thereof. A third memory device is connected to thesecond memory, and stores data received from the second memory device. Amixing unit receives and mixes the stored graphic data and the storedfiltered video data to provide a video output signal V_(OUT).

[0007] In one embodiment, the video signal processing system may beimplemented with a programmable logic module (e.g., a FPCA) andadditional memory units. For example, the first and third memories maybe implemented as RAM external to the programmable logic module, whilethe second memory is located on the programmable logic module andconfigured as a cache to provide fast access. The remaining componentsof the video signal processing system may be located on the programmablelogic module.

[0008] The graphic data may include bitmaps that are provided by amicroprocessor. In this way, for example, transparent buttons may beinserted, while the original video picture associated with the videodata continues to be visible in the background.

[0009] The system may also include a controller that controls theprocessing of the video and graphic signals, and specifically theprogrammable logic module and the memory components. The controller maybe located within the programmable logic module. The controller mayinclude a microprocessor, or receive instructions from an externalmicroprocessor. The microprocessor may control parts of the programexecution or the entire execution of the digital video signal processingprogram.

[0010] The video signal processing system preferably operates in realtime.

[0011] In an alternative embodiment, the video signal processing systemfor processing a video data V_(IN) and graphic data D_(μP), comprising ahorizontal filter that receives the a video data V_(IN) and converts thevideo data V_(IN) into video pictures formatted with a different numberof columns, and provides a horizontally filtered video signal indicativethereof, wherein the horizontal filter buffers individual pixels and/orlines in a first memory device. A second memory device receives andstores the graphic data D_(μP) and the filtered video signal, andprovides stored signals indicative thereof. A third memory device isconnected to the second memory, and stores data received from the secondmemory device. A mixing and filtering unit receives the stored graphicdata and the stored horizontally filtered video data, and verticallyfilters the stored horizontally filtered video data to convert the videodata into video pictures with a different number of lines. The mixingand filtering unit provides a vertically filtered signal indicativethereof and mixes the stored graphic data with the vertically filteredvideo signal to provide a video output signal V_(OUT).

[0012] Significanlty, in this alternative embodiment, the verticalfilter is no longer implemented at the input in the filter block, but atthe output of the so-called layering block. This makes an additionalfilter block memory at the signal/video signal input unnecessary sincethe additional existing memory can be used at the same time.

[0013] In a preferred embodiment, the first memory is configured as afast cache memory and the second memory as working memory in the form ofa random access memory.

[0014] The system of the present invention may be used for an interlaceprogressive conversion. This is needed for future displays with higherresolution. In principle, the same saving applies there, mainly of aCPU, which is situated directly before the vertical filter of the firstarrangement, and of an external memory. The memory saving in this caseis even much greater, since the previous technique requires anadditional half-picture memory for the corresponding signal processing.For example, in the case of the PAL standard, two lines must be interimstored in an external RAM. The second embodiment described herein mayperform the interlace progressive version with the existing CPU andmemory.

[0015] These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of preferred embodiments thereof, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

[0016]FIG. 1 is a block diagram illustration of a first embodiment of avideo signal processing system; and

[0017]FIG. 2 is a block digram illustration of a second embodiment of avideo signal processing system.

DETAILED DESCRIPTION OF THE INVENTION

[0018]FIG. 1 is a block diagram illustration of a first embodiment of avideo signal processing system, which receives a video signal inputV_(IN), and a graphic input signal D_(μP). The video signal input V_(IN)is connected to a filter unit that includes a horizontal filter 11 and avertical filter 12. An external memory 17 (preferably RAM) is associatedwith the filter unit. The filter unit provides a filtered video signalon a line 30 to an intermediate memory 13, which also receives a thegraphic input signal D_(μP). The intermediate memory 13 is connected toanother external memory 16.

[0019] The intermediate memory 13 is also connected to a mixing unit 15,which provides a video output signal V_(OUT). A control unit 14 controlsthe filter unit (i.e., the horizontal filter 11 and the vertical filter12) the memories 13, 16, and 17, and the mixing unit 15. In a preferredembodiment, the horizontal filter 11, vertical filter 12, intermediatememory 13 (cache), mixing unit 15, and control system 14 are integratedinto a programmable logic module (e.g., a FPGA).

[0020] The digital video data of the video input signal V_(IN) arescaled by the horizontal filter 11 and the vertical filter 12 (e.g., thedata are converted into another size relationship to match a displaydevice). For horizontal filtering, generally only a few pixels from thesame line are needed. Since these succeed one another directly in time,only one memory is typically required for a few pixels. However, in thevertical filter 12, the pixels of several lines (e.g., of at least twolines) must be calculated together. Thus the information of at least oneline must be buffered in a memory device. This buffering requires amemory size of at least 710 pixels for the luminous density signal andof at least 360 pixels for each color difference signal. Accordingly, atotal of 1440 pixels (i.e., 720 pixels+(2×360) pixels) have to bestored.

[0021] The data are then written via the intermediate memory 13 (e.g., acache), into an external memory 16 (e.g., RAM). In parallel with this,the graphic data (e.g., bitmaps) for example from a microprocessor (notshown), are written via the fast intermediate memory 13 into theexternal memory 16.

[0022] These pictures are combined with one another in the mixing unit15 (layering block). This is done in such a way that different picturesare calculated together by an adjustable factor, for example, using atechnique often referred to as alpha-blending. The result is transparentpictures that are presented for display on a display device (e.g., a CRTor flat panel display).

[0023] The system 10 is preferably operated in real time, which requiresthat the clock rate of the control system 14 be much higher than theclock rate of the input and output signal.

[0024]FIG. 2 is a block digram illustration of an alternative embodimentvideo signal processing system. The system of FIG. 2 receives andprocesses the video input signal V_(IN), and the graphic input signalD_(μP). Specifically, the video input signal V_(IN) is input to ahorizontal filter 21 that provides a horizontal filtered signal on aline 32. The graphic input signal D_(μP) and the horizontal filteredsignal on the line 32 are input to an intermediate memory 23. Similar tothe first embodiment set forth in FIG. 1, the intermediate memory 23 isconnected to an external memory 26. Furthermore, the intermediate memory23 is connected to a mixing unit 25 and a vertical filter 22, which arepreferably realized in one block as a mixing and filtering unit. Themixing and filtering unit provides a video output signal V_(OUT). Thecomponents (i.e., the horizontal filter, intermediate memory 23,external memory 26, and the mixing and filter units 22 and 25) areconnected via control lines to a control system 24. The control system24, as well as all the other components except the external memory 26,are preferably integrated into a programmable logic module 20 (e.g., aFPGA).

[0025] In the embodiment illustrated in FIG. 2, the vertical filter 22is located at the output of the mixing unit 25 (i.e., layering block),rather than at the input of the filter block as illustrated in FIG. 1.Significantly, in the embodiment illustrated in FIG. 2, the externalmemory 17 is omitted from the filter block since the existing externalmemory 26 (RAM) may be used at the same time.

[0026] The hardware of the mixing unit 25 (layering CPU) may beidentical to that of the first embodiment. Only the control unit 24 nowmanages the correct calculation of the output data through anappropriately modified program execution. The integrated use of themixing unit 25 (layering CPU) for vertical filtering is dynamicallycontrolled by the control system 24 and/or by external instructions froma microprocessor.

[0027] This utilizes the higher clock rate of the CPU as compared to theclock rate of the input and output data. This also makes it possible forthe various picture data, which are to be recalculated, to be read outcorrespondingly fast from the external memory 26 without damaging theirbandwidth. In comparison to the first embodiment, the processingresources for the vertical filter 11 and the additional external memory17 are also saved.

[0028] If this configuration is used for interlace progressiveconversion, the memory saving is even greater. With interlaceprogressive conversion, a full picture with 576 lines is calculated bythe vertical filter 22 from two half pictures, each with 288 lines. Inthis case, therefore, it must be possible to put a half picture, i.e.288 lines, into intermediate storage. In arrangement 1, this must bepossible both in the external memory 17 and in the external memory 16.In arrangement 2, it is sufficient to buffer in the external memory 26.

[0029] In this arrangement the video data associated with the videoinput signal VIN are converted by the horizontal filter 21 into a videopicture with a different number of columns. For this, about 5-6 pixelsare be buffered in the external memory 26. The recalculated video data,together with the graphic data conducted over the graphic input signalD_(μP), are written via the intermediate memory 23 into the externalmemory 26. To superpose two pictures using the mixing unit 25, the videodata of a complete full picture (and the graphic data) must be stored.Consequently, it is desirable if both the mixing and vertical filteringare performed in a single block of the mixing and filtering device 22,25.

[0030] Although the present invention has been shown and described withrespect to several preferred embodiments thereof, various changes,omissions and additions to the form and detail thereof, may be madetherein, without departing from the spirit and scope of the invention.

What is claimed is:
 1. A video signal processing system for processing avideo data V_(IN) and graphic data D_(μP), comprising: a) a filter unit,which receives the video data V_(IN), and horizontally and verticallyfilters the video data V_(IN) to convert the video data V_(IN) intovideo pictures formated with a different number of columns and/or lines,and provides a filtered video signal indicative thereof, wherein saidfilter unit buffers individual pixels and/or lines in a first memorydevice; b) a second memory device that receives and stores the graphicdata D_(μP) and said filtered video signal and provides stored signalsindicative thereof; c) a third memory device that is connected to saidsecond memory, and stores data received from said second memory devices;and d) a mixing unit that receives and mixes said stored graphic dataand said stored filtered video data to provide a video output signalV_(OUT).
 2. The video signal processing system of claim 1 , wherein saidfirst memory device comprises random access memory.
 3. The video signalprocessing system of claim 1 , wherein said second memory is configuredas fast cache memory.
 4. The video signal processing system of claim 3 ,wherein said third memory device comprises random access memory.
 5. Thevideo signal processing system of claim 2 , wherein said graphic graphicdata D_(μP) comprises bitmaps received from a microprocessor.
 6. Thevideo signal processing system of claim 2 , comprising: a controllerthat controls said filter unit, said first, second and third memoriesand said mixing unit to control the processing of said video signalprocesing system.
 7. The video signal processing system of claim 6 ,wherein said video signal processing system operates in real time withthe clock frequency of said controller being higher than the clockfrequency of the signal associated with the video data V_(IN) and saidvideo output signal V_(OUT).
 8. The video signal processing system ofclaim 6 , wherein said controller comprises a microprocessor.
 9. A videosignal processing system for processing a video data V_(IN) and graphicdata D_(μP), comprising: a) a horizontal filter that receives the videodata V_(IN) and converts the video data V_(IN) into video picturesformatted with a different number of columns, and provides ahorizontally filtered video signal indicative thereof, wherein saidhorizontal filter buffers individual pixels and/or lines in a firstmemory device; b) a second memory device that receives and stores thegraphic data D_(μP) and said horizontal filtered video signal andprovides stored signals indicative thereof; c) a third memory devicethat is connected to said second memory, and stores data received fromsaid second memory devices; and d) a mixing and filtering unit thatreceives said stored graphic data and said stored horizontally filteredvideo data, vertically filters said stored horizontally filtered videodata to convert the video data into video pictures with a differentnumber of lines and provide a vertically filtered signal indicativethereof, and mixes said stored graphic data with said verticallyfiltered video signal to provide a video output signal V_(OUT).
 10. Thevideo signal processing system of claim 9 , wherein said second memorydevice is configured as a fast cache memory.
 11. The video signalprocessing system of claim 10 , wherein said third memory devicecomprises random access memory.
 12. The video signal processing systemof claim 10 , wherein the graphic data comprises bitmaps received from amicroprocessor.
 13. The video signal processing system of claim 10 ,comprising: a controller that controls said horizontal filter, saidfirst, second and third memories and said mixing unit to control theprocessing of said video signal procesing system.
 14. The video signalprocessing system of claim 13 , wherein the clock frequency of saidcontroller is higher than the clock frequency of a signal at the videoinput signal V_(IN) and said video output signal V_(OUT).
 15. The videosignal processing system of claim 14 , wherein said controller comprisesa microprocessor.
 16. The video signal processing system of claim 15 ,wherein said video signal processing system is used for interlaceprogressive conversion.
 17. A video signal processing system forprocessing a video data V_(IN) and graphic data D_(μP), comprising: afilter unit, which receives the video data V_(IN) and horizontally andvertically filters the video data V_(IN) to convert the video dataV_(IN) into video pictures formated with a different number of columnsand/or lines, and provides a filtered video signal indicative thereof,wherein said filter unit buffers individual pixels and/or lines in afirst memory device; b) a second memory device that receives and storesthe graphic data D_(μP) and said filtered video signal and providesstored signals indicative thereof; c) a third memory device that isconnected to said second memory, and stores data received from saidsecond memory devices; and d) a mixing unit that receives and mixes saidstored graphic data and said stored filtered video data to provide avideo output signal V_(OUT), which represents a superposition of saidstored graphic data and said stored filtered video data.
 18. A videosignal processing system for processing a video data V_(IN) and graphicdata D_(μP), comprising: a) a horizontal filter that receives the videodata V_(IN) and converts the video data V_(IN) into video picturesformated with a different number of columns, and provides a horizontallyfiltered video signal indicative thereof, wherein said horizontal filterbuffers individual pixels and/or lines in a first memory device; b) asecond memory device that receives and stores the graphic data D_(μP)and said filtered video signal and provides stored signals indicativethereof; c) a third memory device that is connected to said secondmemory, and stores data received from said second memory devices; and d)a mixing and filtering unit that receives said stored graphic data andsaid stored horizontally filtered video data, vertically filters saidstored horizontally filtered video data to convert the video data intovideo pictures with a different number of lines and provide a verticallyfiltered signal indicative thereof, and mixes said stored graphic datawith said vertically filtered video signal to provide a video outputsignal V_(OUT).